A set a scripts to take a design in Verilog and convert it to a factorio blueprint.
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

30 lines
494B

  1. (* techmap_cellteype = "$mul" *)
  2. module $mul(A, B, Y);
  3. parameter A_SIGNED = 0;
  4. parameter B_SIGNED = 0;
  5. parameter A_WIDTH = 4;
  6. parameter B_WIDTH = 4;
  7. parameter Y_WIDTH = 4;
  8. input [A_WIDTH-1:0] A;
  9. input [B_WIDTH-1:0] B;
  10. output [Y_WIDTH-1:0] Y;
  11. foobar #(
  12. .A_SIGNED(B_SIGNED),
  13. .B_SIGNED(A_SIGNED),
  14. .A_WIDTH(B_WIDTH),
  15. .B_WIDTH(A_WIDTH),
  16. .Y_WIDTH(Y_WIDTH)
  17. ) _TECHMAP_REPLACE_.baz (
  18. .A(B),
  19. .B(A),
  20. .Y(Y)
  21. );
  22. wire [1023:0] _TECHMAP_DO_00 = "log fklj;;";
  23. wire _TECHMAP_FAIL_ = 0;
  24. endmodule