A set a scripts to take a design in Verilog and convert it to a factorio blueprint.
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  1. # read design
  2. read_verilog testmod.v
  3. # from pdf docs, page 26
  4. proc
  5. opt
  6. memory
  7. opt
  8. #techmap
  9. techmap -map factorsyniomap.v
  10. opt
  11. dfflibmap -liberty factorsynio.lib
  12. abc -liberty factorsynio.lib
  13. opt
  14. ##### from sample some where
  15. # generic synthesis
  16. #synth -top top #-noalumacc
  17. #techmap -map factorsyniomap.v
  18. # mapping to mycells.lib
  19. #dfflibmap -liberty ../../git/factorsynio/factorsynio.lib
  20. #abc -liberty ../../git/factorsynio/factorsynio.lib
  21. #abc
  22. #clean
  23. # write synthesized design
  24. write_verilog synth.v
  25. write_ilang synth.ilang
  26. write_json synth.json