使用 JavaScript能使本网站更好的工作。
首页
探索
帮助
登录
jmg
/
factorsynio
关注
1
点赞
0
派生
0
代码
工单
0
合并请求
0
版本发布
0
百科
动态
A set a scripts to take a design in Verilog and convert it to a factorio blueprint.
您最多选择25个主题
主题必须以字母或数字开头,可以包含连字符 (-),并且长度不得超过35个字符
1
提交
1
分支
23 KiB
Coq
74.5%
Verilog
25.5%
目录树:
92905c647f
main
分支列表
标签列表
${ item.name }
创建分支
${ searchTerm }
从 '92905c647f'
${ noResults }
HTTPS
ZIP
TAR.GZ
John-Mark Gurney
92905c647f
add first test getting techmap working.. workings fine w/ yosys 0.9
4 年前
.gitignore
add first test getting techmap working.. workings fine w/ yosys 0.9
4 年前
NOTES.md
add first test getting techmap working.. workings fine w/ yosys 0.9
4 年前
cmds.txt
add first test getting techmap working.. workings fine w/ yosys 0.9
4 年前
factorsynio.lib
add first test getting techmap working.. workings fine w/ yosys 0.9
4 年前
factorsyniomap.v
add first test getting techmap working.. workings fine w/ yosys 0.9
4 年前
requirements.txt
add first test getting techmap working.. workings fine w/ yosys 0.9
4 年前
script.ys
add first test getting techmap working.. workings fine w/ yosys 0.9
4 年前
testmod.v
add first test getting techmap working.. workings fine w/ yosys 0.9
4 年前