jmg/factorsynio - factorsynio - Gitea: Git with a cup of tea

A set a scripts to take a design in Verilog and convert it to a factorio blueprint.

add first test getting techmap working.. workings fine w/ yosys 0.9

pirms 4 gadiem

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module top (output reg [3:0] out, input clk, input [3:0] a, input [3:0] b, input [3:0] c);
	always @(posedge clk) begin
		out <= (a * b) + c + (10 + 12);
	end
endmodule