jmg/factorsynio: A set a scripts to take a design in Verilog and convert it to a factorio blueprint. - testmod.v at 92905c647fce1869342022dcee6a60703876941b - factorsynio - Gitea: Git with a cup of tea

A set a scripts to take a design in Verilog and convert it to a factorio blueprint.

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Originalformat Blame Verlauf

module top (output reg [3:0] out, input clk, input [3:0] a, input [3:0] b, input [3:0] c);
	always @(posedge clk) begin
		out <= (a * b) + c + (10 + 12);
	end
endmodule